1. Field of the Invention
The present invention relates to semiconductor structures and methods of forming semiconductor structures, and more particularly to stacked structures and methods of fabricating stacked structures.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high-integration and high-speed goals, dimensions of semiconductor integrated circuits continue to shrink. Various materials and techniques have been proposed to achieve these integration and speed goals and to overcome manufacturing obstacles associated therewith. In order to achieve these goals, a stacked structure including multiple substrates has been proposed to enhance operational speed of circuits.
FIGS. 1A-1D are schematic cross-sectional views showing a process for formation of a prior art stacked structure.
As shown in FIG. 1A, active devices 110 are formed on a substrate 100. An interconnect structure 120 is formed over the substrate 100. The interconnect structure 120 comprises a number of levels of metallization (not shown), each layer of metallization separated from adjacent levels by a layer of dielectric material and interconnected with the adjacent levels by conductive vias.
As shown in FIG. 1B, openings 123 are formed through the interconnect structure 120 and within the substrate 100. After the formation of the openings 123, metal layers 125 are formed within the openings 123 formed in the interconnect structure 120 and the substrate 100, and conductive pad layers 130 are formed on the respective metal layers 125, as shown in FIG. 1C. The metal layers 125 and the pad layers 130 provide a path for electrical connection to the active devices 110 via the metallization layers (not shown) formed within the interconnect structure 120.
After the formation of the metal layers 125 and the pad layers 130, the substrate 100 is flipped and bonded to another substrate 100a by a thermal alloying process, as shown in FIG. 1D. The structures formed over the substrate 100a are similar to those formed over the substrate 100 and are identified with the suffix “a.” The active devices 110 are electrically coupled to the active devices 110a via the interconnects of metal layers 125 and 125a and the pad layers 130 and 130a. 
Referring again to FIG. 1B, in order to form the openings 123 provided for the formation of the metal layers 125 therein, an etch process is performed to remove portions of the levels of metallization within the interconnect structure 120 and then portions of the substrate 100. While removing portions of the substrate 100, the etch process exposes the surfaces of the openings 123, i.e., the substrate 100, to an environment containing metallic ions or other ions released from the exposed metal and dielectric layers (not shown) formed within the interconnect structure 120. The etch process can, therefore, contaminate the substrate 100. In addition, the etch process is complicated because multiple etch steps including varied etchants and processing conditions are used respective to different materials, such as different dielectric layers, low dielectric constant materials, substrate and/or even metal in some case. Accordingly, stacked structures and methods of forming stacked structures are desired.